Received B.E. in Electronics and Communication engineering in 2004 from R.G.P.V, Bhopal, Received M.Tech in VLSI Design from ABV-IIITM, Gwalior in 2006 and Received Ph.D degree in the area of VLSI implementation of DSP Algorithms from JUET, Guna in 2017. In 2006 he was selected for SMDP project, sponsored by MHRD Government of India and joined as Research engineer in the Department of Electronics and Communication engineering, MANIT, Bhopal. In 2007 he joined Jaypee University of Engineering and Technology, Guna, Madhya Pradesh as a Assistance Professor. Currently he serves as the reviewers of various IEEE Transactions, Journal of Circuit, System and Signal Processing, Springer. He has member of various professional bodies like IEEE, IETE. His research interest includes various VLSI architectures design, ASIC and FPGA designs, Image processing. He has published nearly 6 technical papers.

Member of Professional Bodies: IEEE, IETE

Member of editorial board : IEEE Transaction, CSSP springer

SCI Journal Publications

1. Subodh Kumar Singhal and Basant Kumar Mohanty, "Efficient parallel architecture for fixed-coefficient and variable-coefficient FIR filters using distributed arithmetic", Journal of Circuits, Systems, and Computers (JCSC), Vol. 25, No. 7, pp. 1650073-1-1650073-19, March 2016 (SCI).

2. Basant Kumar Mohanty, Promod Kumar Meher, Subodh Kumar Singhal, and M.N.S. Swamy, "A High-Performance VLSI Architecture for Reconfigurable FIR using Distributed Arithmetic", Journal of VLSI Integration, Elsevier, Vol. 54, pp. 37-46, June 2016 (SCI).

3. Basant Kumar Mohanty and Subodh Kumar Singhal, "Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer", Journal of Circuits, Systems, and Signal Processing, Springer, Vol. 35, No. 8, pp. 2958-2971, August 2016 (SCI).

International Conferences

1. Basant Kumar Mohanty, Promod Kumar Meher and Subodh Kumar Singhal "Efficient Architectures for VLSI Implementation of 2-D Discrete Hadamard Transform," IEEE International Symposium on Circuit and Systems (ISCAS-2012), May 20-23, Seoul, Korea.

2. Deepak Shrma, Subodh Kumar Singhal and Ram Mehar Singh Dhariwal "Design of 1.5 GHz Quasilumped Microstrip Highpass Filter" in proceeding of International conference Computational Intelligence, Communication Systems and Networks, pp. 268-270, 23-25 July 2009.

3. Subodh Kumar Singhal, Deepak Shrma, and Ram Mehar Singh Dhariwal "Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs" in proceeding of International conference Computational Intelligence, Communication Systems and Networks, pp. 264-267, 23-25 July 2009.